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dpRam1
- Dual port ram design project developed in Xilinx using VHDL
DW8051
- 8051Ip核内部ram。很多8051iP核都没有内部ram,上传一个希望对大家有用-internel ram of 8051Ip
dual_RAM
- vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
RAM.ZIP
- VHDL CODE FOR RAM AND ROM
BS
- 用EDA设计ROM和RAM及其应用,用VHDL语言编程实现字符、汉字的存取并用点阵显示-ROM and RAM design with the EDA and its applications, using VHDL programming language characters, Chinese characters, access to and use dot-matrix display
jj
- 本题设计一个数字存储示波器,以Xilinx公司20万门FPGA芯片为核心,辅以必要的外围电路(包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块),利用VHDL语言编程,实现了任意波形的单次触发、连续触发和存储回放功能,并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时,将外部输入信号经信号调理模块调节到A/D电路输入范围,经A/D转换后送入FPGA内部的双口RAM进行高速缓存,并将结果通过D/A转换送给通用示波器进行显示,完成了对中、低频信号的实时采样和高频信号的等效采
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
CPU
- 包含CPU每部分器件的编写,通过改写RAM内容,可实现CPU简单运算的仿真-Some devices include the preparation of each CPU, RAM by rewriting the content, enabling easy operation simulation CPU
RamFifoVHDL
- Ram Fifo Core VHDL file
dualportram_vhdl
- 采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化-VHDL hardware descr iption language using the dual-caliber RAM block memory initialization
ram
- 用VHDL描述了RAM的读写,很好的一个小东东,要你好好学习,用于开发RAM-OK,OK,VHDL ,FPGA,RAM,WRITE AND READ ,YOU WILL LIKE IT,ARE YOU?
BoXingFaSheng
- 多功能波形发生器VHDL程序与仿真 功能:实现4种常见波形正弦、三角、锯齿、方波(A、B)的频率、幅度可控输出(方波 --A的占空比也是可控的),可以存储任意波形特征数据并能重现该波形,还可完成 --各种波形的线形叠加输出。 --说明: SSS(前三位)和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号(ss)完成的(AMP的调节范围是0~5V,调节量
ram
- vhdl program for random access memory and sequence detector
vlsiram
- VHDL RAM 16 * 8 source code FPGA
Ram-block-code
- It is a VHDL code for Block RAM
dualportram_asch
- This an asychronous dual port ram-This is an asychronous dual port ram
ram_tb
- ram vhdl module for modelsim and vhdl design
RAM
- ram code in VHDL with its test code
shishi
- 基于FPGA的实时采样系统设计!双口ram典型应用!-FPGA-based real-time sampling system!
ram
- hi this is ram code in vhdl